Trillek Computer Architecture

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Trillek Computer Architecture

Postby Zardoz » Sat Oct 19, 2013 12:10 pm

I was working in specs of a full computer architecture for Trillek, using the RC3200 CPU as base
You can look it here : https://github.com/Zardoz89/Trillek-Computer

Summary :
32 bit RISC like CPU.
I/O devices are memory mapped.
512 KiB + 64Kib of ROM as base configuration. RAM expandable in chunks of 256KiB.
Motherboard includes a Speaker and a Timer devices.
To 32 devices via expansion bus.
Hardware Enumeration, but not hot plug-in of devices.
Can use to 15 Interrupt Requests (IRQs).
Devices can be configured via physical jumper. These jumpers can be read from the software or change the value via software to allow some basic Plug & Play.

Also, with the last retouches that I did to the RC3200 is now more easy to use and understand.

Please read the README before, as I put some advices of how read the documents from the point of view of computer users and point of view of implementation of the VM.
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Re: Trillek Computer Architecture

Postby catageek » Sat Oct 19, 2013 3:56 pm

Is there any reason to put so many registers ? Multiplication of registers in current CPUs is to put data closer than the memory. Since DCPU is virtual, registers are in memory. I don't see the added value.

Same point for the RAM : 16M for each machine does not allow to run many on them in a VM.

Concerning the 32-bit addressing, it is certainly better as it can be easily vectorized. Fixed-length instructions are also a good choice, since DCPU-16 instructions are very difficult to pipeline using vectorization for this reason.
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Re: Trillek Computer Architecture

Postby Zardoz » Sat Oct 19, 2013 4:17 pm

32 register for a 32 bit CPU. Looks that is a not written rule that 32 bit RISC cpus have 32 GPRs. In this case, having many registers allow to use less LOAD & STORE instructions for local vars, but I must agree that they will reside in host ram, but probably inside of the cache at L1 or L2 in the worst case. We could think about reducing it to 16 registers like the ARM cpus.

Who say 16 MiB of RAM ??

There some instructions that accepts one literal value as operand. The literal can be a value inside the 32 bit instruction or can be the next 32 bit value. It can't be avoided if you allow to uses literal values from 0 to (2³² -1), but at least, the most usual values like 0, 1 , -1, 2 , -2, 4 and -4 are inside the literals that not need the next dword. So the majority of the instructions in a program uses 4 bytes and a few can be 8 bytes.
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Re: Trillek Computer Architecture

Postby catageek » Sat Oct 19, 2013 5:18 pm

15Mb come from the hardware description, but I misunderstood that it was to address hardware, not RAM.

A part of the address space could be shared between all the VMs. This feature could be a hardware device, not necessarily a CPU function.

About the instructions on 1 or 2 32 integers, what is important is to have a logical test to distinguish them. In the DCPU-16, 2-words addressing mode was hard to decode. The test should be a simple mask comparison, not a 3-step test.
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Re: Trillek Computer Architecture

Postby Zardoz » Sat Oct 19, 2013 6:07 pm

I did noticed that decoding & executing instructions is pretty more straight forward that in the DCPU-16.

A example :
Code: Select all
LOAD r1 + 1024 , r7 -> 0x0D008207 , 0x00000400
 0xD0008207 -> 0b1101 0000 0000 0000 1000 0110 0000 0111

ram = {..., 0x0D008207, 0x00000400, ...}
i = ram[pc] -> i = 0x0D008207
pc += 4

if (i & 0xC0000000 == 0xC0000000) -> 3 operand instruction
    op1 = reg_table[(i >> 10) & 0x1F]
   
    if (i & 0x00008000 == 0x00008000) -> Operand 2 is a literal value
        if (i & 0x00000200 == 0x00000200) -> Literal is the next dword
          op2 = ram[pc]
          pc += 4
        else
          op2 = (i >> 5) & 0x1F
    else
      op2 = reg_table[(i >> 5)]     

    if (i & 0x10000000 == 0x10000000) -> RAM access instruction
        switch ((i & 0x0FFF0000) >> 16) {
          case 0: // LOAD
            reg_table[i & 0x1F] = ram[op1 + op2]
          ...
        }

The "if" after the "switch/case" can be omitted and use an bigger switch case. Notice that I not need use pointers for the operands as is usual in the DCPU-16 VMs
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Re: Trillek Computer Architecture

Postby Zardoz » Mon Oct 21, 2013 8:12 pm

I made some progress building a VM, but could be very helpful if some try to make a RC3200 assembler, as I need some test code or the CPU and actually typing hex code by hand is slow, error prone and not fun.... :ugeek:
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Re: Trillek Computer Architecture

Postby missPapaya » Tue Oct 22, 2013 2:06 am

IIRC if you want to avoid using the next word as a literal, MIPS got around that by having a "load 16 most significant bits" instruction and a "load 16 least significant bits" instruction.
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Re: Trillek Computer Architecture

Postby Kelmoir » Tue Oct 22, 2013 5:07 am

Well, I'll try to get an assembler up an running. It would be command line, and I would be first focussing on generating opcodes and resoluting labels...
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Re: Trillek Computer Architecture

Postby missPapaya » Tue Oct 22, 2013 5:11 am

also, what does the word suffix mean? For example, "LOAD" and "LOAD.W" Are they 16 bit operations?
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Re: Trillek Computer Architecture

Postby Zardoz » Tue Oct 22, 2013 5:38 am

Kelmoir wrote:Well, I'll try to get an assembler up an running. It would be command line, and I would be first focussing on generating opcodes and resoluting labels...

Thanks !!! :D

missPapaya wrote:also, what does the word suffix mean? For example, "LOAD" and "LOAD.W" Are they 16 bit operations?

LOAD -> Loads a 32 bit value
LOAD.W -> Loads 16 bit value
LOAD.B -> Loads 8 bit value.

missPapaya wrote:IIRC if you want to avoid using the next word as a literal, MIPS got around that by having a "load 16 most significant bits" instruction and a "load 16 least significant bits" instruction.

Not bad idea, but could look a bit more hard to use for the newbies to programming at assembly.
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